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•
Data transfer termination-Data termination signals are required after each data
beat in a data transfer. In a single-beat transaction, the data termination signals also
indicate the end of the tenure; while in burst accesses, the data termination signals
apply to individual beats and indicate the end of the tenure only after the final data
beat. They also indicate whether a condition exists that requires the data phase to be
repeated.
L2 cache address/data-The MPC750 has separate address and data buses for
accessing the L2 cache (not supported in the MPC740).
L2 cache clocklcontrol-These signals provide clocking and control for the L2
cache (not supported in the MPC740).
Interrupts/resets-These signals include the external interrupt signal, checks top
signals, and both soft reset and hard reset signals. They are used to interrupt and,
under various conditions, to reset the processor.
•
Processor status and control-These signals are used to set the reservation
coherency bit, enable the time base, and other functions. They are also used in
conjunction with such resources as secondary caches and the time base facility.
Clock control-These signals determine the system clock frequency. They can also
be used to synchronize multiprocessor systems.
• Test interface-The JTAG (IEEE 1149.1a-1993) interface and the common on-chip
processor (COP) unit provide a serial interface to the system for performing board-
level boundary-scan interconnect tests.
7-2
MPC750 RISC Microprocessor User's Manual
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