Special-Purpose Registers Used By Performance Monitor; Performance Monitor Registers; Monitor Mode Control Register 0 (Mmcro) - Motorola MPC750 User Manual

11.2 Special-Purpose Registers Used by
Performance Monitor
The performance monitor incorporates the SPRs listed in Table 11-1. All of these
supervisor-level registers are accessed through mtspr and mfspr instructions. The
following table shows more information about all performance monitor SPRs.
Table 11-1. Performance Monitor SPRs
SPR Number spr[S·9] II spr[O-4]
Register Name
Access Level
952 Ob11101 11000 MMCRO Supervisor
953 Ob1110111001 PMC1 Supervisor
954 Ob1110111010 PMC2 Supervisor
955 Ob1110111011 SIA Supervisor
956 Ob1110111100 MMCR1 Supervisor
957 Ob1110111101 PMC3 Supervisor
958 Ob11101 11110 PMC4 Supervisor
936 Ob1110101000 UMMCRO User (read only)
937 Ob1110101001
UPMC1
User (read only)
938 Ob1110101010
UPMC2 User (read only)
939 Ob1110101011 USIA User (read only)
940 Ob1110101100 UMMCR1 User (read only)
941 Ob1110101101 UPMC3 User (read only)
942 Ob1110101110 UPMC4 User (read only)
11.2.1 Performance Monitor Registers
This section describes the registers used by the performance monitor.
11.2.1.1 Monitor Mode Control Register 0 (MMCRO)
The monitor mode control register 0 (MMCRO), shown in Figure 11-1, is a 32-bit SPR
provided to specify events to be counted and recorded. MMCRO can be written to only in
supervisor mode. User-level software can read the contents of MMCRO by issuing an
mfspr instruction to UMMCRO, described in Section 11.2.1.2, "User Monitor Mode
Control Register 0 (UMMCRO)."
Chapter 11. Performance Monitor
11-3
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