Motorola MPC750 User Manual page 439

Risc
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D
Denormalized number. A nonzero floating-point number whose exponent
has a reserved value, usually the format's minimum, and whose
explicit or implicit leading significand bit is zero.
Direct-mapped cache. A cache in which each main memory address can
appear in only one location within the cache, operates more quickly
when the memory request is a cache hit.
E
Effective address (EA). The 32- or 64-bit address specified for a load, store,
F
Glossary-4
or an instruction fetch. This address is then submitted to the MMU
for translation to either a physical memory address or an I/O address.
Exception. A condition encountered by the processor that requires special,
supervisor-level processing.
Exception handler. A software routine that executes when an exception is
taken. Normally, the exception handler corrects the condition that
caused the exception, or performs some other meaningful task (that
may include aborting the program that caused the exception). The
address for each exception handler is identified by an exception
vector offset defined by the architecture and a prefix selected via the
MSR.
Exclusive state. MEl state (E) in which only one caching device contains
data that is also in system memory.
Execution synchronization. A mechanism by which all instructions in
execution are architecturally complete before beginning execution
(appearing to begin execution) of the next instruction. Similar to
context synchronization but doesn't force the contents of the
instruction buffers to be deleted and refetched.
Exponent. In the binary representation of a floating-point number, the
exponent is the component that normally signifies the integer power
to which the value two is raised in determining the value of the
represented number. See also Biased exponent.
Fall-through (branch fall-through)-A not-taken branch. On the MPC750,
fall-through branch instructions are removed from the instruction
stream at dispatch. That is, these instructions are allowed to fall
through the instruction queue via the dispatch mechanism, without
either being passed to an execution unit and or given a position in the
completion queue.
MPC750 RISC Microprocessor User's Manual

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