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The MMUs record whether the translation is for an instruction or data access, whether the
processor is in user or supervisor mode and, for data accesses, whether the access is a load
or a store operation. The MMUs use this information to appropriately direct the address
translation and to enforce the protection hierarchy programmed by the operating system.
Section 4.3, "Exception Processing," describes the MSR, which controls some of the
critical functionality of the MMU s.
The figures show how address bits A[20-26] index into the on-chip instruction and data
caches to select a cache set. The remaining physical address bits are then compared with
the tag fields (comprised of bits PA[0-19]) of the two selected cache blocks to determine if
a cache hit has occurred.
In the case of a cache miss on the MPC750, the instruction or data
access is then forwarded to the L2 interface tags to check for an L2 cache hit.
In case of a
miss (and in all cases of an on-chip cache miss on the MPC740) the access is forwarded to
the bus interface unit which initiates an external memory access.
Chapter 5. Memory Management
5-5
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