Table of Contents
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DPn (data bus parity) signals, 7-18
DRTRY (data retry) signal, 7-20, 8-22, 8-25
DSI exception, 4-17
DSISR register, 2-6
DTLB organization, 5-25
Dynamic branch prediction, 6-9
E
EAR (external access register), 2-7
Effective address calculation
address translation, 5-4
branches, 2-35
loads and stores, 2-35, 2-46, 2-51
eieio,2-62
EMI protocol, enforcing memory coherency, 8-26
Enveloped high-priority cache block
push operation, 3-22
Error termination, 8-26
Event
counting, 11-11
selection, 11-12
Exceptions
alignment exception, 4-18
decrementer exception, 4-19
definitions, 4-12
DSI exception, 4-17
enabling and disabling exceptions, 4-10
exception classes, 4-2
exception prefix (IP) bit, 4-13
exception priorities, 4-4
exception processing, 4-7, 4-10
external interrupt, 4-17
FP assist exception, 4-20
FP unavailable exception, 4-19
instruction-related exceptions, 2-37
lSI exception, 4-17
machine check exception, 4-14
performance monitor interrupt, 4-20
program exception, 4-18
register settings
MSR, 4-8, 4-12
SRRO/SRR1,4-7
reset exception, 4-13
returning from an exception handler, 4-11
summary table, 4-3
system call exception, 4-19
system management interrupt, 4-22
terminology, 4-2
thermal management interrupt exception, 4-24
Execution synchronization, 2-36
Execution unit timing examples, 6-18
Execution units, 1-10
External control instructions, 2-64, 8-17, A-28
Index
INDEX
F
Features, list, 1-4
Finish cycle, definition, 6-2
Floating-point model
FEOIFE 1 bits, 4-10
FP arithmetic instructions, 2-42, A-20
FP assist exceptions, 4-20
FP compare instructions, 2-43, A-21
FP load instructions, A-24
FP move instructions, A-25
FP multiply-add instructions, 2-42, A-20
FP operand, 2-30
FP rounding/conversion instructions, 2-43, A-21
FP store instructions, 2-52, A-25
FP unavailable exception, 4-19
FPSCR instructions, 2-44, A-21
IEEE-754 compatibility, 2-28
NI bit in FPSCR, 2-30
Floating-point unit
execution timing, 6-24
latency, FP instructions, 6-34
overview, 1-10, 1-11
Flush block operation, 3-26
FPRn (floating-point registers), 2-3
FPSCR (floating-point status and control register)
FPSCR instructions, 2-44, A-21
FPSCR register description, 2-3
NI bit, 2-29
G
GBL (global) signal, 7-13
GPRn (general-purpose registers), 2-3
Guarded memory bit (G bit), 3-6
H
HIDn (hardware implementation-dependent) registers
HIDO
description, 2-9
doze bit, 10-3
DPM enable bit, 10-2
nap bit, 10-4
HID 1
description, 2-13
PLL configuration, 2-13, 7-30
HRESET (hard reset) signal, 7-23, 8-35
IABR (instruction address breakpoint register), 2-8
ICTC (instruction cache throttling control)
register, 2-21, 10-11
IEEE 1149 .I-compliant interface, 8-37
Illegal instruction class, 2-33
Index-3
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