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o
<-rs :
2
3
:~
~
\~---V
~
,
,
,
,
,
,
D~g r-------~--------_+~
------~--------~
Figure 8-8. Data Bus Arbitration
A qualified data bus grant can be expressed as the following:
QDBG
=
DBG asserted while DBB, DRTRY, and ARTRY (associated with the data
bus operation) are negated.
When a data tenure overlaps with its associated address tenure, a qualified ARTRY
assertion coincident with a data bus grant signal does not result in data bus mastership
(DBB is not asserted). Otherwise, the MPC750 always asserts DBB on the bus clock cycle
after recognition of a qualified data bus grant. Since the MPC750 can pipeline transactions,
there may be an outstanding data bus transaction when a new address transaction is retried.
In this case, the MPC750 becomes the data bus master to complete the previous transaction.
8.4.1.1 USing the DBB Signal
The DBB signal should be connected between masters if data tenure scheduling is left to
the masters. Optionally, the memory system can control data tenure scheduling directly
with DBG. However, it is possible to ignore the DBB signal in the system if the DBB input
is not used as the final data bus allocation control between data bus masters, and if the
memory system can track the start and end of the data tenure. If DBB is not used to signal
the end of a data tenure, DBG is only asserted to the next bus master the cycle before the
cycle that the next bus master may actually begin its data tenure, rather than asserting it
earlier (usually during another master's data tenure) and allowing the negation of DBB to
be the final gating signal for a qualified data bus grant. Even if DBB is ignored in the
system, the MPC750 always recognizes its own assertion of DBB, and requires one cycle
after data tenure completion to negate its own DBB before recognizing a qualified data bus
grant for another data tenure. If DBB is ignored in the system, it must still be connected to
a pull-up resistor on the MPC750 to ensure proper operation.
8-20
MPC750 RISC Microprocessor User's Manual
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