Table of Contents
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Instruction cache
configuration, 3-4
instruction cache block fill operations, 3-21
organization, 3-5
Instruction cache throttling, 10-10
Instruction timing
examples
cache hit, 6-12
cache miss, 6-15
execution unit, 6-18
instruction flow, 6-8
memory performance considerations, 6-27
overview, 6-3
terminology, 6-1
Instructions
branch address calculation, 2-53
branch instructions, 6-9, 6-18, 6-20, A-25
cache control instructions, 9-4
cache management instructions, A-27
classes, 2-32
condition register logical, 2-54, A-26
defined instructions, 2-33
external control instructions, 2-64, A-28
floating-point
arithmetic, 2-42, A-20
compare, 2-43, A-21
FP load instructions, A-24
FP move instructions, A-25
FP rounding and conversion, 2-43, A-21
FP status and control register, 2-44
FP store instructions, A-25
FPSCR instructions, A-21
multiply-add, 2-42, A-20
illegal instructions, 2-33
instruction cache throttling, 10-10
instruction flow diagram, 6-10
instruction serialization, 6-17
instruction serialization types, 6-17
instruction set summary, 2-31
instructions not implemented, B-1
integer
arithmetic, 2-38, A-17
compare, 2-39, A-18
load, A-22
load/store mUltiple, A-23
load/store string, A-24
load/store with byte reverse, A-23
logical, 2-40, A-18
rotate and shift, 2-40, A-19
store, A-23
integer instructions, 6-33
isync,4-12
latency summary, 6-31
Index-4
INDEX
load and store
address generation
floating-point, 2-51
integer, 2-46
byte reverse instructions, 2-49, A-23
floating-point load, A-24
floating-point move, 2-44, A-25
floating-point store, 2-51
handling misalignment, 2-45
integer load, 2-46, A-22
integer multiple, 2-49
integer store, 2-47, A-23
memory synchronization, 2-59, 2-61, A-24
multiple instructions, A -23
string instructions, 2-50, A-24
lookaside buffer management instructions, A-28
memory control instructions, 2-62, 2-66
memory synchronization instructions, 2-59,
2-61, A-24
PowerPC instructions, list, A-I. A-9, A-17
processor control instructions, 2-56, 2-60, 2-65,
A-27
reserved instructions, 2-34
rfi,4-11
segment register manipulation instructions, A-28
SLB management instructions, A-28
stwcx., 4-12
support for Iwarxlstwcx., 8-36
sync, 4-12
system linkage instructions, 2-55, A-26
TLB management instructions, A-28
tlbie,2-67
tlbsync, 2-67
trap instructions, 2-55, A-26
INT (interrupt) signal, 7-21, 8-35
Integer arithmetic instructions, 2-38, A-17
Integer compare instructions, 2-39, A-18
Integer load instructions, 2-46, A-22
Integer logical instructions, 2-40, A-IS
Integer rotate/shift instructions, 2-40, A-19
Integer store gathering, 6-26
Integer store instructions, 2-47, A-23
Integer unit execution timing, 6-24
Interrupt, external, 4-17
lSI exception, 4-17
isync, 2-62, 4-12
ITLB organization, 5-25
K
Kill block operation, 3-26
MPC750 RISC Microprocessor User's Manual
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