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Table 7-1 describes the transfer encodings for an MPC750 bus master.
Table 7-1. Transfer Type Encodings for MPC750 Bus Master
MPC750 Bus
Transaction
60x Bus
Master
Source
TTO
Tn
TT2
IT3
IT4
Specification
Transaction
Transaction
Command
Address on Iy
1
dcbst
0
0
0
0
0
Clean block
Address only
Address only
1
dcbf
a
0
1
a
a
Flush block
Address only
Address only
1
sync
a
1
0
a
a
sync
Address only
Address only
1
dcbz or dcbi
a
1
1
a
0
Kill block
Address only
Address only
1
eieio
1
a
a
a
0
eieio
Address only
Single-beat
ecowx
1
0
1
a
0
External control
Single-beat
write (nonGBL)
word write
write
N/A
N/A
1
1
0
0
0
TLB invalidate
Address only
Single-beat
eciwx
1
1
1
0
0
External control
Single-beat
read (nonGBL)
word read
read
N/A
N/A
0
0
0
0
1
lwarx
Address only
reservation set
N/A
N/A
0
0
1
0
1
ReservEid
-
N/A
N/A
0
1
0
0
1
tlbsync
Address only
N/A
N/A
0
1
1
0
1
icbi
Address only
N/A
N/A
1
X
X
0
1
Reserved
-
Single-beat
Caching-inhibited
0
0
0
1
0
Write-with-flush
Single-beat
write
or write-through
write or burst
store
Burst
Cast-out, or
0
0
1
1
0
Write-with-kill
Burst
(nonGBL)
snoop copyback
Single-beat
Caching-inhibited
0
1
0
1
0
Read
Single-beat
read
load or instruction
read or burst
fetch
Burst
Load miss, store
0
1
1
1
0
Read-with-intent-
Burst
miss, or
to-modify
instruction fetch
Single-beat
stwcx.
1
0
0
1
0
Write-with-flush-
Single-beat
write
atomic
write
N/A
N/A
1
0
1
1
0
Reserved
N/A
Single-beat
Iwarx (caching-
1
1
0
1
0
Read-atomic
Single-beat
read
inhibited load)
read or burst
Burst
lwarx
1
1
1
1
0
Read-with-intent-
Burst
(load miss)
to-modify-atomic
N/A
N/A
0
0
0
1
1
Reserved
-
Chapter 7. Signal Descriptions
7-9
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