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The setting of the ICE bit must be preceded by an isyne instruction to prevent the cache
from being enabled or disabled in the middle of an instruction fetch. In addition, the cache
must be globally flushed before it is disabled to prevent coherency problems when it is
re-enab1ed. The icbi instruction is not affected by disabling the instruction cache.
3.4.1.6 Instruction Cache Locking
The contents of the instruction cache can be locked by setting the instruction cache lock bit,
HIDO[ILOCK]. An instruction fetch that hits in a locked instruction cache is serviced by
the cache. However, all accesses that miss in the locked cache are propagated to the L2
cache or 60x bus as single-beat transactions. Note that the CI signal always reflects the state
of the caching-inhibited memory/cache access attribute (the I bit) independent of the state
of HIDO[ILOCK].
The setting of the ILOCK bit must be preceded by an isyne instruction to prevent the
instruction cache from being locked during an instruction fetch.
3.4.2 Cache Control Instructions
The PowerPC architecture defines instructions for controlling both the instruction and data
caches (when they exist). The cache control instructions, debt, debtst, debz, debst, debf,
debi, and icbi, are intended for the management of the local L1 and L2 caches. The
MPC750 interprets the cache control instructions as if they pertain only to its own L1 or L2
caches. These instructions are not intended for managing other caches in the system (except
to the extent necessary to maintain coherency).
The MPC750 does not snoop cache control instruction broadcasts, except for debz when
M
=
1. The debz instruction is the only cache control instruction that causes a broadcast on
the 60x bus (when M
=
1)
to maintain coherency. All other data cache control instructions
(debi, debf, debst and debz) are not broadcast, unless broadcast is enabled through the
HIDO[ABE] configuration bit. Note that debi, debf, debst and debz do broadcast to the
MPC750's L2 cache, regardless of HIDO[ABE]. The icbi instruction is never broadcast.
3.4.2.1 Data Cache Block Touch (dcbt) and
Data Cache Block Touch for Store (dcbtst)
The Data Cache Block Touch (debt) and Data Cache Block Touch for Store (debtst)
instructions provide potential system performance improvement through the use of
software-initiated prefetch hints. The MPC750 treats these instructions identically (that is,
a debtst instruction behaves exactly the same as a debt instruction on the MPC750). Note
that PowerPC implementations are not required to take any action based on the execution
of these instructions, but they may choose to prefetch the cache block corresponding to the
effective address into their cache.
The MPC750 loads the data into the cache when the address hits in the TLB or the BAT, is
permitted load access from the addressed page, is not directed to a direct-store segment, and
is directed at a cacheab1e page. Otherwise, the MPC750 treats these instructions as no-ops.
The data brought into the cache as a result of this instruction is validated in the same manner
Chapter 3. L 1 Instruction and Data Cache Operation
3-15
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