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Table 4-4. MSR Bit Settings (Continued)
Bit(s)
Name
Description
22
BE
Branch trace enable
0
The processor executes branch instructions normally.
1
The processor generates a branch type trace exception when a branch instruction executes
successfully.
23
FE1
IEEE floating-point exception mode 1 (see Table 4-5).
24
-
Reserved. This bit corresponds to the AL bit of the POWER architecture.
25
IP
Exception prefix. The setting of this bit specifies whether an exception vector offset is prepended
with Fs or Os. In the following description, nnnnn is the offset of the exception.
0
Exceptions are vectored to the physical address OxOOOn_nnnn.
1
Exceptions are vectored to the physical address OxFFF n_nnnn.
26
IR
Instruction address translation
0
Instruction address translation is disabled.
1
Instruction address translation is enabled.
For more information see Chapter 5, "Memory Management."
27
DR
Data address translation
0
Data address translation is disabled.
1
Data address translation is enabled.
For more information see Chapter 5, "Memory Management."
28
-
Reserved. Full function
1
29
PM
Performance monitor marked mode
0
Process is not a marked process.
1
Process is a marked process.
MPC750-specific; defined as reserved by the PowerPC architecture. For more information about
the performance monitor, see Section 4.5.13, "Performance Monitor Interrupt (OxOOFOO)."
30
RI
Indicates whether system reset or machine check exception is recoverable.
0
Exception is not recoverable.
1
Exception is recoverable.
The RI bit indicates whether from the perspective of the processor, it is safe to continue (that is,
processor state data such as that saved to SRRO is valid), but it does not guarantee that the
interrupted process is recoverable.
31
LE
Little-endian mode enable
0
The processor runs in big-endian mode.
1
The processor runs in little-end ian mode.
Note:
1Full function reserved bits are saved in SRR1 when an exception occurs; partial function reserved
bits are not saved.
The IEEE floating-point exception mode bits (FEO and FEI) together define whether
floating-point exceptions are handled precisely, imprecisely, or whether they are taken at
all. As shown in Table 4-5, if either FEO or FEl are set, theMPC750 treats exceptions as
precise. MSR bits are guaranteed to be written to SRRI when the first instruction of the
exception handler is encountered. For further details, see Chapter 6, "Exceptions," of The
Programming Environments Manual.
Chapter 4. Exceptions
4-9
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