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8.9 IEEE 1149.1 a-1993 Compliant Interface
The MPC750 boundary-scan interface is a fully-compliant implementation of the IEEE
1149.1a-1993 standard. This section describes the MPC750's IEEE 1149.1a-1993 (JTAG)
interface.
8.9.1 JTAG/COP Interface
The MPC750 has extensive on-chip test capability including the following:
•
Debug control/observation (COP)
•
Boundary scan (standard IEEE 1149.1a-1993 (JTAG) compliant interface)
•
Support for manufacturing test
The COP and boundary scan logic are not used under typical operating conditions. Detailed
discussion of the MPC750 test functions is beyond the scope of this document; however,
sufficient information has been provided to allow the system designer to disable the test
functions that would impede normal operation.
The JTAG/COP interface is shown in Figure 8-21. For more information, refer to IEEE
Standard Test Access Port and Boundary Scan Architecture IEEE STD 1149-1 a-1993.
- - - - - - ' TOI (Test Data Input)
- - - - + \
TMS (Test Mode Select)
- - - - - - . l
TCK (Test Clock Input)
. . . - - - - - - - - j
TOO (Test Data Output)
- - - - - - . l
TRST (Test Reset)
Figure 8-21. IEEE 1149.1a-1993 Compliant Boundary Scan Interface
8.10 USing Data Bus Write Only
The MPC750 supports split-transaction pipelined transactions. It supports a limited
out-of-order capability for its own pipelined transactions through the data bus write only
(DBWO) signal. When recognized on the clock of a qualified DBG, the assertion ofDBWO
directs the MPC750 to perform the next pending data write tenure (if any), even if a pending
read tenure would have normally been performed because of address pipelining. The
DBWO signal does not change the order of write tenures with respect to other write tenures
from the same MPC750. It only allows that a write tenure be performed ahead of a pending
read tenure from the same MPC750.
Chapter 8. System Interface Operation
8-37
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