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Bit settings for MMCR1 are shown in Table 11-3. The corresponding events are described
in Section 11.2.1.5, "Performance Monitor Counter Registers (PMC 1-PMC4)."
Table 11-3. MMCR1 Bit Settings
Bits
Name
Description
0-4
PMC3SELECT
PMC3 input selector. 32 events selectable. See Table 11-7 for defined selections.
5-9
PMC4SELECT
PMC4 input selector. 32 events selectable. See Table 11-8 for defined selections.
10-31
-
Reserved
MMCR1 can be accessed with the mtspr and mfspr instructions using SPR 956. User-level
software can read the contents of MMCR1 by issuing an mfspr instruction to UMMCR1,
described in Section 11.2.1.4, "User Monitor Mode Control Register 1 (UMMCR1)."
11.2.1.4 User Monitor Mode Control Register 1 (UMMCR1)
The contents of MMCRI are reflected to UMMCRl, which can be read by user-level
software. UMMCRI can be accessed with the mfspr instructions using SPR 940.
11.2.1.5 Performance Monitor Counter Registers (PMC1-PMC4)
PMCI-PMC4, shown in Figure 11-3, are 32-bit counters that can be programmed to
generate interrupt signals when they overflow.
Counter Value
o
1
31
Figure 11-3. Performance Monitor Counter Registers (PMC1-PMC4)
The bits contained in the PMC registers are described in Table 11-4 .
Table 11-4. PMCn Bit Settings
Bits
Name
Description
0
OV
Overflow. When this bit is set, it indicates this counter has reached its maximum value.
1-31
Counter value
Indicates the number of occurrences of the specified event.
Counters overflow when the high-order bit (the sign bit) becomes set; that is, they reach the
value 2147483648 (Ox8000_0000). However, an interrupt is not signaled unless both
MMCRO[ENINT] and either PMClINTCONTROL or PMCINTCONTROL in the
MMCRO register are also set as appropriate.
Note that the interrupts can be masked by clearing MSR[EE]; the interrupt signal condition
may occur with MSR[EE] cleared, but the exception is not taken until MSR[EE] is set.
Setting MMCRO[DISCOUNT] forces counters to stop counting when a counter interrupt
occurs.
11-6
MPC750 RiSe Microprocessor User's Manual
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