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Instructions cannot be dispatched to an execution unit unless there is a vacancy in the
completion queue. Branch instructions that do not update the CTR or LR are removed from
the instruction stream and do not take an entry in the completion queue. Instructions that
update the CTR and LR follow the same dispatch and completion procedures as non-branch
instructions, except that they are not issued to an execution unit.
Completing an instruction commits execution results to architected registers (GPRs, FPRs,
LR, and CTR). In-order completion ensures the correct architectural state when the
MPC750 must recover from a mispredicted branch or any exception. Retiring an instruction
removes it from the completion queue.
For a more detailed discussion of instruction completion, see Section 6.3.3, "Instruction
Dispatch and Completion Considerations."
1.2.2.4 Independent Execution Units
In addition to the BPU, the MPC750 provides the five execution units described in the
following sections.
1.2.2.4.1 Integer Units (IUs)
The integer units lUI and IU2 are shown in Figure 1-1. The lUI can execute any integer
instruction; the IU2 can execute any integer instruction except multiplication and division
instructions. Each IU has a single-entry reservation station that can receive instructions
from the dispatch unit and operands from the GPRs or the rename buffers.
Each IU consists of three single-cycle subunits-a fast adder/comparator, a subunit for
logical operations, and a subunit for performing rotates, shifts, and count-leading-zero
operations. These subunits handle all one-cycle arithmetic instructions; only one subunit
can execute an instruction at a time.
The lUI has a 32-bit integer multiplier/divider as well as the adder, shift, and logical units
of the IU2. The multiplier supports early exit for operations that do not require full 32-
x
32-bit multiplication.
Each IU has a dedicated result bus (not shown in Figure 1-1) that connects to rename
buffers.
1.2.2.4.2 Floating-Point Unit (FPU)
The FPU, shown in Figure 1-1, is designed such that single-precision operations require
only a single pass, with a latency of three cycles. As instructions are dispatched to the FPU's
reservation station, source operand data can be accessed from the FPRs or from the FPR
rename buffers. Results in turn are written to the rename buffers and are made available to
subsequent instructions. Instructions pass through the reservation station in dispatch order.
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MPC750 RISC Microprocessor User's Manual
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