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Split-transaction. A transaction with independent request and response
tenures.
Split-transaction bus. A bus that allows address and data transactions from
different processors to occur independently.
Static branch prediction. Mechanism by which software (for example,
compilers) can hint to the machine hardware about the direction a
branch is likely to take.
Superscalar machine. A machine that can issue multiple instructions
concurrently from a conventional linear instruction stream.
Supervisor mode. The privileged operation state of a processor.
In
supervisor mode, software, typically the operating system, can
access all control registers and can access the supervisor memory
space, among other privileged operations.
Synchronization. A process to ensure that operations occur strictly in order.
See Context synchronization and Execution synchronization.
Synchronous exception. An exception that is generated by the execution of
a particular instruction or instruction sequence. There are two types
of synchronous exceptions, precise and imprecise.
System memory. The physical memory available to a processor.
T
Tenure. A tenure consists of three phases: arbitration, transfer, termination.
Glossary-12
There can be separate address bus tenures and data bus tenures.
TLB (translation lookaside buffer) A cache that holds recently-used page
table entries.
Throughput. The measure of the number of instructions that are processed
per clock cycle.
Transaction. A complete exchange between two bus devices. A transaction
is minimally comprised of an address tenure; one or more data
tenures may be involved in the exchange.
Transfer termination. Signal that refers to both signals that acknowledge the
transfer of individual beats (of both single-beat transfer and
individual beats of a burst transfer) and to signals that mark the end
of the tenure.
MPC750 RISC Microprocessor User's Manual
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