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Although multiple exception conditions can map to a single exception vector, a more
specific condition may be determined by examining a register associated with the
exception-for example, the DSISR and the FPSCR. Additionally, some exception
conditions can be enabled or disabled explicitly by software.
The PowerPC architecture requires that exceptions be handled in program order; therefore,
although a particular implementation may recognize exception conditions out of order, they
are handled in order. When an instruction-caused exception is recognized, any unexecuted
instructions that appear earlier in the instruction stream, including any that are
undispatched, are required to complete before the exception is taken, and any exceptions
those instructions cause must also be handled first. Likewise, asynchronous, precise
exceptions are recognized when they occur, but are not handled until the instructions
currently in the completion queue successfully retire or generate an exception, and the
completion queue is emptied.
Unless a catastrophic condition causes a system reset or machine check exception, only one
exception is handled at a time. For example, if one instruction encounters multiple
exception conditions, those conditions are handled sequentially. After the exception handler
handles an exception, the instruction processing continues until the next exception
condition is encountered. Recognizing and handling exception conditions sequentially
guarantees that exceptions are recoverable.
When an exception is taken, information about the processor state before the exception was
taken is saved in SRRO and SRRI. Exception handlers should save the information stored
in SRRO and SRRI early to prevent the program state from being lost due to a system reset
and machine check exception or to an instruction-caused exception in the exception
handler, and before enabling external interrupts.
The PowerPC architecture supports four types of exceptions:
• Synchronous, precise-These are caused by instructions. All instruction-caused
exceptions are handled precisely; that is, the machine state at the time the exception
occurs is known and can be completely restored. This means that (excluding the trap
and system call exceptions) the address of the faulting instruction is provided to the
exception handler and that neither the faulting instruction nor subsequent
instructions in the code stream will complete execution before the exception is
taken. Once the exception is processed, execution resumes at the address of the
faulting instruction (or at an alternate address provided by the exception handler).
When an exception is taken due to a trap or system call instruction, execution
resumes at an address provided by the handler.
• Synchronous, imprecise-The PowerPC architecture defines two imprecise
floating-point exception modes, recoverable and nonrecoverable. Even though the
MPC750 provides a means to enable the imprecise modes, it implements these
modes identically to the precise mode (that is, enabled floating-point exceptions are
always precise).
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MPC750 RISC Microprocessor User's Manual
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