Motorola MPC750 User Manual page 277

Table 6-8. Load and Store Instructions (Continued)
Mnemonic Primary Extended Unit Cycles Serialization
stwcx. 31 150 LSU 8:8
Execution
stwu
37 -
LSU
2:1 -
stwux
31 183 LSU 2:1
-
stwx 31 151 LSU 2:1
-
tlbie
31 306 LSU 3:4
1
Execution
Notes:
1
For cache-ops, the first number indicates the latency in finishing a single instruction; the second indicates the
throughput for back-to-back cache-ops. Throughput
may
be larger than the initial latency as more cycles
may
be
needed to complete the instruction to the cache, which stays busy keeping subsequent cache-ops from executing.
2
The throughput number of 6 cycles for dcbz assumes it is to nonglobal (M
=
0) address space. For global address
space, throughput is at least 11 cycles.
3
Load/store multiple/string instruction cycles are represented as a fixed number of cycles plus a variable number of
cycles, where
n
is the number of words accessed by the instruction.
6-38 MPC750 RISC Microprocessor User's Manual