Table of Contents
Advertisement
10.2.1.3 Doze Mode
Doze mode disables most functional units but maintains cache coherency by enabling the
bus interface unit and snooping. A snoop hit causes the MPC750 to enable the data cache,
copy the data back to memory, disable the cache, and fully return to the doze state.
•
Most functional units disabled
•
Bus snooping and time baseldecrementer still enabled
•
Doze mode sequence
-
Set doze bit
(HIDO[8] =
I), clear nap and sleep bits
(HIDO[9]
and
HIDO[
I 0]
=
0)
-
MPC750 enters doze mode after several processor clocks
Several methods of returning to full-power mode
-
Assert INT, SMI, MCP, decrementer, performance monitor, or thermal
management interrupts
-
Assert hard reset or soft reset
• Transition to full-power state takes no more than a few processor cycles
•
PLL running and locked to SYSCLK
10.2.1.4 Nap Mode
The nap mode disables the MPC750 but still maintains the phase-locked loop (PLL), delay
locked loop (DLL), L2CLK_OUTA and L2CLK_OUTB output signals, and the time basel
decrementer. The time base can be used to restore the MPC750 to full-power state after a
programmed amount of time. To maintain data coherency, bus snooping is disabled for nap
and sleep modes through a hardware handshake sequence using the quiesce request
(QREQ) and quiesce acknowledge (QACK) signals. The MPC750 asserts the QREQ signal
to indicate that it is ready to disable bus snooping. When the system has ensured that
snooping is no longer necessary, it will assert QACK and the MPC750 will enter the nap
mode. If the system determines that a bus snoop cycle is required, QACK is deasserted to
the MPC750 for at least eight bus clock cycles, and the MPC750 will then be able respond
to a snoop cycle. Assertion of QACK following the snoop cycle will again disable the
MPC750's snoop capability. The MPC750's power dissipation while in nap mode with
QACK deasserted is the same as the power dissipation while in doze mode.
Note that when in nap mode the DLL should be kept locked to enable a quick recovery to
full-power mode without having to wait for the DLL to re-Iock. Additionally, an L2ZZ
signal is provided by the MPC750's L2 cache interface to drive external SRAM into a low
power mode when the nap or sleep modes are invoked. The L2ZZ signal is enabled by
setting the L2CR[CTL] bit to 1. Note that if bus snooping is to be performed through
deassertion of the QACK signal, the L2CR[CTL] bit should always be cleared to O.
•
Time baseldecrementer still enabled
• Most functional units disabled
•
All nonessential input receivers disabled
Chapter 10. Power and Thermal Management
10-3
-
Advertisement
Table of Contents
