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If
SRESET is asserted, the processor is first put in a recoverable state. To do this, the
MPC750 allows any instruction at the point of completion to either complete or take an
exception, blocks completion of any following instructions and allows the completion
queue to drain. The state before the exception occurred is then saved as specified in the
PowerPC architecture and instruction fetching begins at the system reset interrupt vector
offset, OxOOlOO. The vector address on a soft reset depends on the setting of MSR[IP]
(either OxOOOO_OlOO or OxFFFO_OlOO). Soft resets are third in priority, after hard reset and
machine check. This exception is recoverable provided attaining a recoverable state does
not generate a machine check.
SRESET is an edge-sensitive signal that can be asserted and deasserted asynchronously,
provided the minimum pulse width specified in the hardware specifications is met.
Asserting SRESET causes the MPC750 to take a system reset exception. This exception
modifies the MSR, SRRO, and SRR1, as described in The Programming Environments
Manual. Unlike hard reset, soft reset does not directly affect the states of output signals.
Attempts to use SRESET during a hard reset sequence or while the JTAG logic is non-idle
cause unpredictable results.
A hard reset is initiated by asserting HRESET. Hard reset is used primarily for power-on
reset (POR) (in which case
TRST
must also be asserted), but can also be used to restart a
running processor. The HRESET signal must be asserted during power up and must remain
asserted for a period that allows the PLL to achieve lock and the internal logic to be reset.
This period is specified in the hardware specifications. The MPC750 internal state after the
hard reset interval is defined in Table 2-19.
If
HRESET is asserted for less than this amount
of time, the results are not predictable.
If
HRESET is asserted during normal operation, all
operations cease and the machine state is lost.
The MPC750 implements HIDO[NHR], which helps software distinguish a hard reset from
a soft reset. Because this bit is cleared by a hard reset, but not by a soft reset, software can
set this bit after a hard reset and tell whether a subsequent reset is a hard or soft reset by
examining whether this bit is still set. See Section 2.1.2.2, "Hardware Implementation-
Dependent Register 0."
4.5.2 Machine Check Exception (Ox00200)
The MPC750 implements the machine check exception as defined in the PowerPC
architecture (OEA). It conditionally initiates a machine check exception after an address or
data parity error occurred on the bus or in either the Ll or L2 cache, after receiving a
qualified transfer error acknowledge (TEA) indication on the MPC750 bus, or after the
machine check interrupt (MCP) signal had been asserted. As defined in the OEA, the
exception is not taken if MSR[ME] is cleared, in which case the processor enters checkstop
state.
4-14
MPC750 RISC Microprocessor
User's
Manual
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