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Table 4-5. IEEE Floating-Point Exception Mode Bits
FEO FE1
Mode
0
0
Floating-point exceptions disabled
0
1
Imprecise nonrecoverable. For this setting, the MPC750 operates in floating-point precise mode.
1
0
Imprecise recoverable. For this setting, the MPC750 operates in floating-point precise mode.
1
1
Floating-point precise mode
4.3.1 Enabling and Disabling Exceptions
When a condition exists that may cause an exception to be generated, it must be determined
whether the exception is enabled for that condition.
• IEEE floating-point enabled exceptions (a type of program exception) are ignored
when both MSR[FEO] and MSR[FEl] are cleared. If either bit is set, all IEEE
enabled floating-point exceptions are taken and cause a program exception.
• Asynchronous, maskable exceptions (such as the external and decrementer
interrupts) are enabled by setting MSR[EE]. When MSR[EE]
=
0, recognition of
these exception conditions is delayed. MSR[EE] is cleared automatically when an
exception is taken to delay recognition of conditions causing those exceptions.
• A machine check exception can occur only if the machine check enable bit,
MSR[ME], is set.
If
MSR[ME] is cleared, the processor goes directly into checkstop
state when a machine check exception condition occurs. Individual machine check
exceptions can be enabled and disabled through bits in the HIDO register, which is
described in Table 4-8.
•
System reset exceptions cannot be masked.
4.3.2 Steps for Exception Processing
After it is determined that the exception can be taken (by confirming that any instruction-
caused exceptions occurring earlier in the instruction stream have been handled, and by
confirming that the exception is enabled for the exception condition), the processor does
the following:
1. SRRO is loaded with an instruction address that depends on the type of exception.
See the individual exception description for details about how this register is used
for specific exceptions.
2. SRRl[I-4, 10-15] are loaded with information specific to the exception type.
3. SRRl[5-9, 16-31] are loaded with a copy of the corresponding MSR bits.
Depending on the implementation, reserved bits may not be copied.
4-10
MPC750 RISC Microprocessor User's Manual
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