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Figure 9-10 shows a burst read-write-write memory access sequence when the L2 cache
interface is configured with late-write SRAM.
SRAMClk
L2CE
L2WE
SRAMAddress
SRAMMemory
SRAMData
Note:
WQ is the last previous write that was queued in the late-write RAM.
Figure 9-10. Burst Read-Write-Write L2 Cache Access (Late-Write SRAM)
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MPC750 RISC Microprocessor User's Manual
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