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that is modified on the MPC750's cache, the access is delayed so the MPC750 can
copy the modified data to memory.
•
Write-through-Store operations to memory marked write-through always update
both system memory and the on-chip cache on cache hits. Because valid cache
contents always match system memory marked write-through, cache hits from other
devices do not cause modified data to be copied back as they do for locations marked
write-back. However, all write operations are passed to the bus, which can limit
performance. Load operations that miss the on-chip cache must wait for the external
store operation.
Write-through configuration is useful when cached data must agree with external
memory (for example, video memory), when shared (global) data may be needed
often, or when it is undesirable to allocate a cache block on a cache miss.
Chapter 3, "LI Instruction and Data Cache Operation," describes the caches, memory
configuration, and snooping in detail.
6.5.2 Effect of TLB Miss
If a page address translation is not in a TLB, the MPC750 hardware searches the page tables
and updates the TLB when a translation is found. Table 6-2 shows the estimated latency for
the hardware TLB load for different cache configurations and conditions.
Table 6-2. TLB Miss Latencies
L 1 Condition
L2 Condition
ProcessorlL2
Processor/System Bus
Estimated Latency
(Instruction and Data)
Clock Ratio
Clock Ratio
(Cycles)
100% cache hit
-
-
-
7
100% cache miss
100% cache hit
1:1
-
13
100% cache miss
100% cache hit
1.5:1
-
18
100% cache miss
100% cache hit
2:1
-
20
100% cache miss
100% cache miss
1:1
2.5:1 (6:3:3:3 memory)
62
100% cache miss
100% cache miss
1 :1
4:1 (5:2:2:2 memory)
77
The PTE table search assumes a hit in the first entry of the primary PTEG.
6-28
MPC750 RISC Microprocessor User's Manual
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