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Simplified mnemonics are provided for the mftb instruction so it can be coded with the
TBR name as part of the mnemonic rather than requiring it to be coded as an operand. See
Appendix F, "Simplified Mnemonics," in The Programming Environments Manual for
simplified mnemonic examples and for simplified mnemonics for Move from Time Base
(mftb) and Move from Time Base Upper (mftbu), which are variants of the mftb
instruction rather than of mfspr. The mftb instruction serves as both a basic and simplified
mnemonic. Assemblers recognize an mftb mnemonic with two operands as the basic form,
and an mftb mnemonic with one operand as the simplified form. Note that the MPC750
ignores the extended opcode differences between mftb and mfspr by ignoring bit 25 and
treating both instructions identically.
Implementation Notes-The following information is useful with respect to using the
time base implementation in the MPC750:
The MPC750 allows user-mode read access to the time base counter through the use
of the Move from Time Base (mftb) and the Move from Time Base Upper (mftbu)
instructions. As a 32-bit PowerPC implementation, the MPC750 can access TBU
and TBL only separately, whereas 64-bit implementations can access the entire TB
register at once.
• The time base counter is clocked at a frequency that is one-fourth that of the bus
clock. Counting is enabled by assertion of the time base enable (TBE) input signal.
2.3.5.2 Memory Synchronization Instructions-VEA
Memory synchronization instructions control the order in which memory operations are
completed with respect to asynchronous events, and the order in which memory operations
are seen by other processors or memory access mechanisms. See Chapter 3, "Ll Instruction
and Data Cache Operation," for more information about these instructions and about related
aspects of memory synchronization.
In addition to the sync instruction (specified by VISA), the VEA defines the Enforce
In-Order Execution of
110
(eieio) and Instruction Synchronize (isync) instructions. The
number of cycles required to complete an eieio instruction depends on system parameters
and on the processor's state when the instruction is issued. As a result, frequent use of this
instruction may degrade performance slightly.
Chapter 2. MPC750 Processor Programming Model
2-61
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