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INTONBITTRANS - - - - - - ,
RTCSELECT - - - - ,
o
1
2
3
4
5 6
7
8
9 10
PMC21NTCONTROL
PMC11NTCONTROL
THRESHOLD
PMCTRIGGER
PMC1SELECT
15 16 17 18 19
25 26
Figure 11-1. Monitor Mode Control Register 0 (MMCRO)
PMC2SELECT
31
This register must be cleared at power up. Reading this register does not change its
contents. Table 11-2 describes the bits of the MMCRO register.
Table 11-2. MMCRO Bit Settings
Bit
Name
Description
0
DIS
Disables counting unconditionally.
0
The values of the PMCn counters can be changed by hardware.
1
The values of the PMCn counters cannot be changed by hardware.
1
DP
Disables counting while in supervisor mode.
0
The PMCn counters can be changed by hardware.
1
If the processor is in supervisor mode (MSR[PR] is cleared), the counters are not
changed by hardware.
2
DU
Disables counting whHe in user mode.
0
The PMCn counters can be changed by hardware.
1
If the processor is in user mode (MSR[PR] is set), the PMCn counters are not
changed by hardware.
3
OMS
Disables counting while MSR[PM] is set.
0
The PMCn counters can be changed by hardware.
1
If MSR[PM] is set, the PMCn counters are not changed by hardware.
4
DMR
Disables counting while MSR[PM] is zero.
0
The PMCn counters can be changed by hardware.
1
If MSR[PM] is cleared, the PMCn counters are not changed by hardware.
5
ENINT
Enables performance monitor interrupt signaling.
0
Interrupt signaling is disabled.
1
Interrupt signaling is enabled.
Cleared by hardware when a performance monitor interrupt is signaled. To re-enable
these interrupt signals, software must set this bit after servicing the performance
monitor interrupt. The IPL ROM code clears this bit before passing control to the
operating system.
6
DISCOUNT
Disables counting of PMCn when a performance monitor interrupt is signaled (that is,
((PMCnlNTCONTROL
~
1) &
(PMCn[O].~
1) & (ENINT
~
1)) or the occurrence of an
enabled time base transition with ((INTONBITTRANS
~1)
& (ENINT
~
1)).
0
Signaling a performance monitor interrupt does not affect counting status of
PMCn.
1
The signaling of a performance monitor interrupt prevents changing of PMC1
counter. The PMCn counter does not change if PMC2COUNTCTL
~
O.
Because a time base signal could have occurred along with an enabled counter
overflow condition, software should always reset INTONBITTRANS to zero, if the value
in INTONBITTRANS was a one.
11-4
MPC750 RISC Microprocessor User's Manual
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