Motorola MPC750 User Manual page 176

pushes; WT is negated for ecowx transactions. Since the write-through status is not
meaningful for reads, the MPC750 uses the WT signal during read transactions to indicate
that the transaction is an instruction fetch (WT negated), or not an instruction fetch (WT
asserted).
The CI signal reflects the caching-inhibited/allowed status (the complement of the I bit) of
the transaction as determined by the MMU address translation even if the Ll caches are
disabled or locked. CI is always asserted for eciwx/ecowx bus transactions independent of
the address translation.
The GBL signal reflects the memory coherency requirements (the complement of the M bit)
of the transaction as determined by the MMU address translation. Castout and snoop
copy-back operations (TT[O-4]
=
00110) are generally marked as nonglobal (GBL
negated) and are not snooped (except for reservation monitoring). Other masters, however,
may perform DMA write operations with this encoding but marked global (GBL asserted)
and thus must be snooped.
Table 3-6 summarizes the address and transfer attribute information presented on the bus
by the MPC750 for various master or snoop-related transactions.
Table 3-6. Address/Transfer Attribute Summary
Bus Transaction A[O-31] TT[O-4] TBST TSIZ[o-2] GBl
WT
cr
Instruction fetch operations:
Burst (caching-allowed)
PA[0-28]II ObOOO
01110
0 010
,M
1
1*
Single-beat read
PA[0-28]II ObOOO
01010 1
000
,M
1
,1
(caching-inhibited or cache
disabled)
Data cache operations:
Cache block fill (due to load or
PA[0-28]II ObOOO A 1110 0 010
,M
0
1*
store miss)
Castout
CA[0-26]II ObOOOOO
00110
0
010 1 1 1*
(normal replacement)
Push (cache block push due to PA[0-26]II ObOOOOO 00110 0 010 1 0 1*
dcbf/dcbst)
Snoop copyback
CA[0-261110bOOOOO 00110 0 010
1
0
1*
Data cache bypass operations:
Single-beat read PA[0-31]
A 1010 1 SSS
,M
0
,1
(caching-inhibited or cache
disabled)
Single-beat write
PA[0-31] 0001 0 1 SSS
,M ,W
,1
(caching-inhibited, write-through,
or cache disabled)
Special instructions:
Chapter 3. L 1 Instruction and Data Cache Operation
3-29