Motorola MPC750 User Manual page 314

Risc
Hide thumbs Also See for MPC750:
Table of Contents

Advertisement

ADDRESS TENURE
~
____________
~A~
______________
~
r
\
ARBITRATION
TERMINATION
INDEPENDENT ADDRESS AND DATA
\
__
----------------~A~------------------_
r
,
DATA TENURE
I
ARBITRATION
I
SINGLE-BEAT TRANSFER
I
TERMINATION
I
Figure 8-3. Overlapping Tenures on the MPC750 Bus for a Single-Beat Transfer
The basic functions of the address and data tenures are as follows:
Address tenure
-
Arbitration: During arbitration, address bus arbitration signals are used to gain
mastership of the address bus.
-
Transfer: After the MPC750 is the address bus master, it transfers the address on
the address bus. The address signals and the transfer attribute signals control the
address transfer. The address parity and address parity error signals ensure the
integrity of the address transfer.
-
Termination: After the address transfer, the system signals that the address tenure
is complete or that it must be repeated.
Data tenure
-
Arbitration: To begin the data tenure, the MPC750 arbitrates for mastership of
the data bus.
-
Transfer: After the MPC750 is the data bus master, it samples the data bus for
read operations or drives the data bus for write operations. The data parity and
data parity error signals ensure the integrity of the data transfer.
-
Termination: Data termination signals are required after each data beat in a data
transfer. Note that in a single-beat transaction, the data termination signals also
indicate the end of the tenure, while in burst accesses, the data termination
signals apply to individual beats and indicate the end of the tenure only after the
final data beat.
The MPC750 generates an address-only bus transfer during the execution of the dcbz
instruction (and for the dcbi, dcbf, dcbst, sync, and eieio instructions, if HIDO[ABE] is
enabled), which uses only the address bus with no data transfer involved. Additionally, the
MPC750's retry capability provides an efficient snooping protocol for systems with
multiple memory systems (including caches) that must remain coherent.
Chapter 8. System Interface Operation
8-7

Advertisement

Table of Contents
loading

Table of Contents