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Appendix A
PowerPC Instruction Set Listings
This appendix lists the MPC750 microprocessor's instruction set as well as the additional
PowerPC instructions not implemented in the MPC750. Instructions are sorted by
mnemonic, opcode, function, and form. Also included in this appendix is a quick reference
table that contains general information, such as the architecture level, privilege level, and
form, and indicates if the instruction is 64-bit and optional. Note that the MPC750 is a 32-
bit microprocessor, and doesn't implement any 64-bit instructions.
Note that split fields, that represent the concatenation of sequences from left to right, are
shown in lowercase. For more information refer to Chapter 8, "Instruction Set," in The
Programming Environments Manual.
A.1 Instructions Sorted by Mnemonic
Table A-I lists the instructions implemented in the PowerPC architecture in alphabetical
order by mnemonic.
Key:
Reserved bits
Table A-1. Complete Instruction List Sorted by Mnemonic
Name
0
5
6
7
8
9 1011 121314151617 18 192021 22232425262728293031
add x
31
D
A
B
bE
266
Rc
addcx
31
D
A
B
OE
10
Rc
addex
31
D
A
B
bE
138
Rc
addi
14
D
A
SIMM
addic
12
D
A
SIMM
addic.
13
D
A
SIMM
addis
15
D
A
SIMM
31
D
A
"",:nh'
~:
234
Rc
31
D
A
202
Rc
addmex
addzex
Appendix A. PowerPC Instruction Set Listings
A-1
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