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Figure 8-6. Address Bus Transfer
8.3.2.1 Address Bus Parity
The MPC750 always generates 1 bit of correct odd-byte parity for each of the 4 bytes of
address when a valid address is on the bus. The calculated values are placed on the AP[0-3]
outputs when the MPC750 is the address bus master. If the MPC750 is not the master and
TS and GBL are asserted together (qualified condition for snooping memory operations),
the calculated values are compared with the AP[0-3] inputs. If there is an error, and address
parity checking is enabled (HIDO[EBA] set to 1), a machine check exception is generated.
An address bus parity error causes a checks top condition if MSR[ME] is cleared to O. For
more information about checkstop conditions, see Chapter 4, "Exceptions."
8.3.2.2 Address Transfer Attribute Signals
The transfer attribute signals include several encoded signals such as the transfer type
(TT[0-4]) signals, transfer burst (TBST) signal, transfer size (TSIZ[0-2]) signals,
write-through (WT) , and cache inhibit (CI). Section 7.2.4, "Address Transfer Attribute
Signals," describes the encodings for the address transfer attribute signals.
8.3.2.2.1 Transfer Type (TT[0-4]) Signals
Snooping logic should fully decode the transfer type signals if the GBL signal is asserted.
Slave devices can sometimes use the individual transfer type signals without fully decoding
the group. For. a complete description of the encoding for TT[0-4], refer to Table 8-1 and
Table 8-2.
8.3.2.2.2 Transfer Size (TSIZ[0-2]) Signals
The TSIZ[0-2] signals indicate the size of the requested data transfer as shown in Table 8-1.
The TSIZ[0-2] signals may be used along with TBST and A[29-31] to determine which
portion of the data bus contains valid data for a write transaction or which portion of the
bus should contain valid data for a read transaction. Note that for a burst transaction (as
Chapter 8. System Interface Operation
8-13
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