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7.2.3.2.2 Address Bus Parity (AP[O-3])-lnput
Following are the state meaning and timing comments for the AP[0--3] input signal on the
MPC750.
State Meaning
AssertedlNegated-Represents odd parity for each of the 4 bytes of
the physical address for snooping operations. Detected even parity
causes the processor to take a machine check exception or enter the
checkstop state if address parity checking is enabled in the HIDO
register; see Section 2.1.2.2, "Hardware Implementation-Dependent
Register 0."
Timing Comments AssertionlNegation-The same asA[0-31].
7.2.4 Address Transfer Attribute Signals
The transfer attribute signals are a set of signals that further characterize the transfer-such
as the size of the transfer, whether it is a read or write operation, and whether it is a burst
or single-beat transfer. For a detailed description of how these signals interact, see
Section 8.3.2, "Address Transfer."
Note that some signal functions vary depending on whether the transaction is a memory
access or an I/O access.
7.2.4.1 Transfer Type (TT[O-4])
The transfer type (TT[0--4]) signals consist of five input/output signals on the MPC750. For
a complete description of TT[0--4] signals and for transfer type encodings, see Table 7-1.
7.2.4.1.1 Transfer Type (TT[O-4])-Output
Following are the state meaning and timing comments for the TT[0--4] output signals on
the MPC750.
State Meaning
AssertedlNegated-Indicates the type of transfer in progress.
Timing Comments AssertionlNegationlHigh Impedance-The same as A[0--31].
7.2.4.1.2 Transfer Type (TT[O-4])-lnput
Following are the state meaning and timing comments for the TT[0--4] input signals on the
MPC750.
State Meaning
AssertedlNegated-Indicates the type of transfer in progress (see
Table 7-2).
Timing Comments AssertionlNegation-The same as A[0--31].
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MPC750 RISC Microprocessor User's Manual
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