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3.4 Cache Control
The MPC750's L1 caches are controlled by programming specific bits in the HIDO
special-purpose register and by issuing dedicated cache control instructions. Section 3.4.1,
"Cache Control Parameters in HIDO," describes the HIDO cache control bits, and
Section 3.4.2, "Cache Control Instructions," describes the cache control instructions.
3.4.1 Cache Control Parameters in HIDO
The HIDO special-purpose register contains several bits that invalidate, disable, and lock
the instruction and data caches. The following sections describe these facilities.
3.4.1.1 Data Cache Flash Invalidation
The data cache is automatically invalidated when the MPC750 is powered up and during a
hard reset. However, a soft reset does not automatically invalidate the data cache. Software
must use the HIDO data cache flash invalidate bit (HIDO[DCFID if data cache invalidation
is desired after a soft reset. Once HIDO[DCFI] is set through an mtspr operation, the
MPC750 automatically clears this bit in the next clock cycle (provided that the data cache
is enabled in the HIDO register).
Note that some PowerPC microprocessors accomplish data cache flash invalidation by
setting and clearing HIDO[DCFI] with two consecutive mtspr instructions (that is, the bit
is not automatically cleared by the microprocessor). Software that has this sequence of
operations does not need to be changed to run on the MPC750.
3.4.1.2 Data Cache Enabling/Disabling
The data cache may be enabled or disabled by using the data cache enable bit, HIDO[DCE].
HIDO[DCE] is cleared on power-up, disabling the data cache.
When the data cache is in the disabled state (HIDO[DCE]
=
0), the cache tag state bits are
ignored, and all accesses are propagated to the L2 cache or 60x bus as single-beat
transactions. Note that the CI (cache inhibit) signal always reflects the state of the
caching-inhibited memory/cache access attribute (the I bit) independent of the state of
HIDO[DCE]. Also note that disabling the data cache does not affect the translation logic;
translation for data accesses is controlled by MSR[DR].
The setting of the DCE bit must be preceded by a syne instruction to prevent the cache from
being enabled or disabled in the middle of a data access. In addition, the cache must be
globally flushed before it is disabled to prevent coherency problems when it is re-enabled.
Snooping is not performed when the data cache is disabled.
The debz instruction will cause an alignment exception when the data cache is disabled.
The touch load (debt and debtst) instructions are no-ops when the data cache is disabled.
Other cache operations (caused by the debf, debst, and debi instructions) are not affected
Chapter 3. L 1 Instruction and Data Cache Operation
3-13
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