Motorola MPC750 User Manual page 97

Bits MMCRO[26-31] specify events associated with PMC2, as shown in Table 2-11.
Table 2-11. PMC2 Events-MMCRO[26-31] Select Encodings
Encoding Description
000000 Register holds current value.
000001 Number of processor cycles
000010 Number of completed instructions. Does not include folded branches.
000011 Number of transitions from 0 to 1 of specified bits in time base lower register. Bits are specified
through RTCSElECT (MMRCO[7-8]). 00
=
15, 01
=
19, 10
=
23,11
=
31.
000100 Number of instructions dispatched. 0, 1, or 2 instructions per cycle
000101 Number of eieio instructions completed
000110 Number of cycles spent performing table search operations for the ITlS
000111 Number of accesses that hit the l2
001000 Number of valid instruction EAs delivered to the memory subsystem
001001 Number of times that the address of an instruction being completed matches the address in the IASR
001010 Number of loads that miss the l1 and have latencies that exceeded the threshold value
001011 Number of branches that are unresolved when processed
001100 Number of cycles the dispatcher stalls due to a second unresolved branch in the instruction stream
All others Reserved. May be used in a later revision.
Bits MMCR1[0-4] specify events associated with PMC3, as shown in Table 2-12.
Table 2-12. PMC3 Events-MMCR1[0-41 Select Encodings
Encoding Description
00000 Register holds current value.
00001
Number of processor cycles
00010 Number of completed instructions, not including folded branches.
00011 Number of transitions from 0 to 1 of specified bits in the time base lower register. Bits are specified
through RTCSElECT (MMRCO[7-8]). 0
=
47, 1
=
51, 2
=
55, 3
=
63.
00100 Number of instructions dispatched. 0, 1, or 2 per cycle.
00101 Number of l1 data cache misses
00110
Number of DTlB misses
00111 Number of l2 data misses
01000 Number of taken branches, including predicted branches.
01001 Number of transitions between marked and unmarked processes while in user mode. That is, the
number of MSR[PM] toggles while the processor is in user mode.
01010 Number of store conditional instructions completed
2-18
MPC750 RISC Microprocessor User's Manual