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o
2
3
4
5
6
7
8
9
10
11
1
~
• • •
1
c==J
Fetch'
Instruction
Oueue
Completion
Oueue
2 add
3fadd
3
2
1
0
1
~
In dispatch entry (100/101)
. . . Execute
_
Complete (In CO)
I
I
[IO
1
1
. .
In retirement entry (COO/C01)
~
1
1
~Address ~====:=====~====:====)1>----'---""-
1 1 1-
Data
---'---r--«,---,-_-r'X~--,-_-r"X
V-
-
i
-
I
'-r---""""'I /
"--r
r.16~~~d~"I---'----'---'----'---
17fadd'
I
I
8add'i
I
9 add '
I
5
4
3
2
3
2
3
3
2
2
0
0
3
7
6
10 add
'I
11 add'
' I
12fadd'
!
13fadd'i
7
6
9
8
9
8
7
7
6
6
, Instructions 5 and 6 are not in the 10 in clock cycle 5. Here, the fetch stage shows cache latency.
Figure 6-6. Instruction Timing-Cache Miss
6.3.2.4 L2 Cache Access Timing Considerations (MPC750 Only)
If an instruction fetch misses both the BTIC and the on-chip instruction cache, the MPC750
next looks in the L2 cache. If the requested instructions are there, they are burst into the
Chapter 6. Instruction Timing
6-15
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