Motorola MPC750 User Manual page 184

These classifications are discussed in greater detail in Section 4.2, "Exception Recognition
and Priorities." For a better understanding of how the MPC750 implements precise
exceptions, see Chapter 6, "Instruction Timing." Exceptions implemented in the MPC750,
and conditions that cause them, are listed in Table 4-2.
Table 4-2. Exceptions and Conditions
Exception Type
Vector Offset
Causing Conditions
(hex)
Reserved 00000
-
System reset 00100 Assertion of either HRESET or SRESET or at power-on reset
Machine check 00200 Assertion of TEA during a data bus transaction, assertion of MCP, or an
address, data, or L2 bus parity error. MSR[ME] must be set.
OSI
00300
As specified in the PowerPC architecture. For TLB misses on load, store, or
cache operations, a OSI exception occurs if a page fault occurs.
lSI 00400 As defined by the PowerPC architecture
External interrupt 00500 MSR[EE] = 1 and INT is asserted
Alignment 00600 A floating-point load/store, stmw, stwcx., Imw, Iwarx, eciwx, or ecowx
instruction operand is not word-aligned.
.
A multiple/string load/store operation is attempted in little-endian mode
.
An operand of a dcbz instruction is on a page that is write-through or
cache-inhibited for a virtual mode access.
An attempt to execute a dcbz instruction occurs when the cache is
disabled.
Program 00700 As defined by the Power PC architecture
Floating-point 00800 As defined by the PowerPC architecture
unavailable
Oecrementer 00900 As defined by the PowerPC architecture, when the most-significant bit of the
DEC register changes from 0 to 1 and MSR[EE] = 1
Reserved OOAOO-OOBFF
-
System call OOCOO Execution of the System Call (sc) instruction
Trace 00000 MSR[SE] =1 or a branch instruction is completing and MSR[BE] =1. The
MPC750 differs from the OEA by not taking this exception on an isync.
Reserved OOEOO The MPC750 does not generate an exception to this vector. Other PowerPC
processors may use this vector for floating-pOint assist exceptions.
Reserved 00E10-00EFF
-
Performance monitor OOFOO The limit specified in PMCn is met and MMCRO[ENINT] = 1 (MPC750-specific)
Instruction address 01300 IABR[0-29] matches EA[0-29] of the next instruction to complete, IABR[TE]
breakpoint matches MSR[IR], and IABR[BE] = 1 (MPC750-specific)
System management 01400 MSR[EE] = 1 and SMI is asserted (MPC750-specific)
interrupt
Chapter 4. Exceptions
4-3