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the system power controller can enable snooping by the MPC750 by deasserting the QACK
signal for at least eight bus clock cycles, after which the MPC750 is capable of snooping
bus transactions. The reassertion of QACK following the snoop transactions will cause the
MPC750 to reenter the nap power state.
8.8 Processor State Signals
This section describes the MPC750's support for atomic update and memory through the
use of the Iwarx/stwcx. opcode pair, and includes a description of the TLBISYNC input.
8.8.1 Support for the Iwarx/stwcx. Instruction Pair
The Load Word and Reserve Indexed (Iwarx) and the Store Word Conditional Indexed
(stwcx.) instructions provide a means for atomic memory updating. Memory can be
updated atomically by setting a reservation on the load and checking that the reservation is
still valid before the store is performed. In the MPC750, the reservations are made on behalf
of aligned, 32-byte sections of the memory address space.
The reservation (RSRV) output signal is driven synchronously with the bus clock and
reflects the status of the reservation coherency bit in the reservation address register; see
Chapter 3, "Ll Instruction and Data Cache Operation," for more information. For
information about timing, see Section 7.2.9.7.3, "Reservation (RSRV)-Output."
8.8.2 TlBISYNC Input
The TLBISYNC input allows for the hardware synchronization of changes to MMU tables
when the MPC750 and another DMA master share the same MMU translation tables in
system memory.
It
is asserted by a DMA master when it is using shared addresses that could
be changed in the MMU tables by the MPC750 during the DMA master's tenure.
The TLBISYNC input, when asserted to the MPC750, prevents the MPC750 from
completing any instructions past a tlbsync instruction. Generally, during the execution of
an eciwx or ecowx instruction by the MPC750, the selected DMA device should assert the
MPC750's TLBISYNC signal and maintain it asserted during its DMA tenure if it is using
a shared translation address. Subsequent instructions by the MPC750 should include a sync
and tIbsync instruction before any MMU table changes are performed. This will prevent
the MPC750 from making table changes disruptive to the other master during the DMA
period.
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MPC750 RISC Microprocessor User's Manual
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