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properly managed in cases where the regenerated ABB may not properly track the ABB
signal on the bus. If the MPC750's ABB signal is ignored by the system, it must be
connected to a pull-up resistor to ensure proper operation. Additionally, the MPC750 will
not qualify a bus grant during the cycle that TS is asserted on the bus by any master. Address
bus arbitration without the use of the ABB signal requires that every assertion of TS be
acknowledged by an assertion of AACK while the processor is not in sleep mode.
8.3.2 Address Transfer
During the address transfer, the physical address and all attributes of the transaction are
transferred from the bus master to the slave device(s). Snooping logic may monitor the
transfer to enforce cache coherency; see discussion about snooping in Section 8.3.3,
"Address Transfer Termination."
The signals used in the address transfer include the following signal groups:
• Address transfer start signal: transfer start (TS)
• Address transfer signals: address bus (A[0-31]), and address parity (AP[0-3])
• Address transfer attribute signals: transfer type (TT[0-4]), transfer size
(TSIZ[O-2]), transfer burst (TBST), cache inhibit (CI), write-through (WT), and
global (GBL)
Figure 8-6 shows that the timing for all of these signals, except TS, is identical. All of the
address transfer and address transfer attribute signals are combined into the ADDR+
grouping in Figure 8-6. The TS signal indicates that the MPC750 has begun an address
transfer and that the address and transfer attributes are valid (within the context of a
synchronous bus). The MPC750 always asserts TS coincident with ABB. As an input, TS
need not coincide with the assertion of ABB on the bus (that is, TS can be asserted with, or
on, a subsequent clock cycle after ABB is asserted; the MPC750 tracks this transaction
correctly).
In Figure 8-6, the address transfer occurs during bus clock cycles 1 and 2 (arbitration occurs
in bus clock cycle 0 and the address transfer is terminated in bus clock 3). In this diagram,
the address bus termination input, AACK, is asserted to the MPC750 on the bus clock
following assertion ofTS (as shown by the dependency line). This is the minimum duration
of the address transfer for the MPC750; the duration can be extended by delaying the
assertion of AACK for one or more bus clocks.
8-12
MPC750 RISC Microprocessor User's Manual
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