Table of Contents
Advertisement
Timing Comments Assertion-May occur any time to indicate the MPC750 is free to
take data bus mastership. It is not sampled until TS is asserted.
Negation-May occur at any time to indicate the MPC750 cannot
assume data bus mastership.
7.2.6.2 Data Bus Write Only (DBWO)-Input
The data bus write only (DBWO) signal is an input-only signal on the MPC750. Following
are the state meaning and timing comments for the DBWO signal.
State Meaning
Asserted-Indicates that the MPC750 may run the data bus tenure
for an outstanding write address even if a read address is pipelined
before the write address. Refer to Section 8.10, "Using Data Bus
Write Only," for detailed instructions for using DBWO.
Negated-Indicates that the MPC750 must run the data bus tenures
in the same order as the address tenures.
Timing Comments Assertion-Must occur no later than a qualified DBG for an
outstanding write tenure. DBWO is sampled by the MPC750 on the
clock of a qualified
iSBG.
If no write requests are pending, the
MPC750 will ignore DBWO and assume data bus ownership for the
next pending read request.
Negation-May occur any time after a qualified DBG and before the
next assertion of DBG.
7.2.6.3 Data Bus Busy (DBB)
The data bus busy (DBB) signal is both an input and output signal on the MPC750.
7.2.6.3.1 Data Bus Busy (DBB)-Output
Following are the state meaning and timing comments for the DBB output signal.
State Meaning
Asserted-Indicates that the MPC750 is the data bus master. The
MPC750 always assumes data bus mastership if it needs the data bus
and is given a qualified data bus grant (see DBG).
Negated-Indicates that the MPC750 is not using the data bus.
Timing Comments Assertion-Occurs during the bus clock cycle following a qualified
DBG.
Negation-Occurs for a minimum of one-half bus clock cycle
(dependent on clock mode) following the assertion of the final TA.
High Impedance-Occurs after DBB is negated.
7.2.6.3.2 Data Bus Busy (DBB)-Input
Following are the state meaning and timing comments for the DBB input signal.
State Meaning
Asserted-Indicates that another device is bus master.
7-16
Negated-Indicates that the data bus is free (with proper
qualification, see DBG) for use by the MPC750.
MPC750 RISC Microprocessor User's Manual
Advertisement
Table of Contents
