Data Bus Tenure; Data Bus Arbitration - Motorola MPC750 User Manual

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Figure 8-7. Snooped Address Cycle with ARTRY
8.4 Data Bus Tenure
This section describes the data bus arbitration, transfer, and termination phases defined by
the MPC750 memory access protocol. The phases of the data tenure are identical to those
of the address tenure, underscoring the symmetry in the control of the two buses.
8.4.1 Data Bus Arbitration
Data bus arbitration uses the data arbitration signal group-DBG, DBWO, and DBB.
Additionally, the combination of TS and
IT[O-4]
provides information about the data bus
request to external logic.
The TS signal is an implied data bus request from the MPC750; the arbiter must qualify TS
with the transfer type
(IT)
encodings to determine if the current address transfer is an
address-only operation, which does not require a data bus transfer (see Figure 8-7). If the
data bus is needed, the arbiter grants data bus mastership by asserting the DBG input to the
MPC750. As with the address bus arbitration phase, the MPC750 must qualify the DBG
input with a number of input signals before assuming bus mastership, as shown in
Figure 8-8.
Chapter 8. System Interface Operation
8-19