Motorola MPC750 User Manual page 137

Table 2-48. PowerPC Encodings (Continued)
SPR
1
Register Name Access
mfspr/mtspr
Decimal spr[5-9] spr[0-4]
XER 1 00000
00001 User (UISA) Both
Notes:
1
The order of the two 5-bit halves of the SPR number is reversed compared with actual
instruction coding. For mtspr and mfspr instructions, the SPR number coded in assembly
language does not appear directly as a 1 O-bit binary number in the instruction. The number
coded is split into two 5-bit halves that are reversed in the instruction, with the high-order five
bits appearing in bits 16-20 of the instruction and the low-order five bits in bits 11-15.
2
The TB registers are referred to as TBRs rather than SPRs and can be written to using the
mtspr instruction in supervisor mode and the TBR numbers here. The TB registers can be read
in user mode using either the mftb or mtspr instruction and specifying TBR 268 for TBl and
SPR 269 for TBU.
Encodings for the MPC750-specific SPRs are listed in Table 2-49.
Table 2-49 SPR Encodings for MPC750-Defined Registers (mfspr)
Register
SPR
1
Name
Access mfspr/mtspr
Decimal spr[5-9] spr[0-4]
DABR
1013 11111 10101 User Both
HIDO 1008 11111 10000 Supervisor Both
HIDI 1009 11111 10001 Supervisor Both
IABR 1010
11111 10010 Supervisor Both
ICTC 1019 11111 11011 Supervisor Both
L2CR 1017 11111 11001 Supervisor Both
MMCRO 952 11101 11000
Supervisor Both
MMCRI 956 11101 11100 Supervisor Both
PMCI 953 11101 11001 Supervisor Both
PMC2 954 11101
11010 Supervisor Both
PMC3 957 11101 11101 Supervisor Both
PMC4 958 11101 11110 Supervisor
Both
SIA 955 11101
11011 Supervisor Both
THRMI 1020 11111 11100 Supervisor Both
THRM2 1021 11111 11101
Supervisor Both
THRM3 1022 11111
11110 Supervisor Both
UMMCRO 936 11101 01000 User
mfspr
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