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Machine check exceptions are enabled when MSR[ME]
=
1; this is described in the
following section, Section 4.5.2.1, "Machine Check Exception Enabled (MSR[ME]
=
1)."
If
MSR[ME]
=
0 and a machine check occurs, the processor enters the checkstop state.
Checkstop state is described in Section 4.5.2.2, "Checks top State (MSR[ME]
=
0)."
4.5.2.1 Machine Check Exception Enabled (MSR[ME]
=
1)
Machine check exceptions are enabled when MSR[ME]
=
1. When a machine check
exception is taken, registers are updated as shown in Table 4-9.
Table 4-9. Machine Check Exception-Register Settings
Register
Setting Description
SRRO
On a best-effort basis the MPC750 can set this to an EA of some instruction that was executing or about to
SRRI
MSR
be executing when the machine check condition occurred.
0-10 Cleared
11
Set when an L2 data cache parity error is detected, otherwise zero
12
Set when MCP signal is asserted, otherwise zero
13
Set when TEA signal is asserted, otherwise zero
14
Set when a data bus parity error is detected, otherwise zero
15
Set when an address bus parity error is detected, otherwise zero
16-31 MSR[16-31]
POW 0
FP
0
BE
0
DR
0
ILE
-
ME
0
FEI
0
PM
0
EE
0
FEO
0
IP
-
RI
0
PR
0
SE
0
IR
0
LE
Set to value of ILE
Note that to handle another machine check exception, the exception handler should set MSR[ME] as soon
as it is practical after a machine check exception is taken. Otherwise, subsequent machine check excep-
tions cause the processor to enter the checkstop state.
The machine check exception is usually unrecoverable in the sense that execution cannot
resume in the context that existed before the exception. If the condition that caused the
machine check does not otherwise prevent continued execution, MSR[ME] is set to allow
the processor to continue execution at the machine check exception vector address.
Typically, earlier processes cannot resume; however, operating systems can use the
machine check exception handler to try to identify and log the cause of the machine check
condition.
When a machine check exception is taken, instruction fetching resumes at offset Ox00200
from the physical base address indicated by MSR[IP].
4.5.2.2 Checkstop State (MSR[ME]
=
0)
If
MSR[ME]
=
0 and a machine check occurs, the processor enters the checks top state.
When a processor is in checks top state, instruction processing is suspended and generally
cannot resume without the processor being reset. The contents of all latches are frozen
within two cycles upon entering checks top state.
4-16
MPC750
RISC
Microprocessor User's
Manual
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