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5.1.1 Memory Addressing
A program references memory using the effective (logical) address computed by the
processor when it executes a load, store, branch, or cache instruction, and when it fetches
the next instruction. The effective address is translated to a physical address according to
the procedures described in Chapter 7, "Memory Management," in The Programming
Environments Manual, augmented with information in this chapter. The memory
subsystem uses the physical address for the access.
For a complete discussion of effective address calculation, see Section 2.3.2.3, "Effective
Address Calculation."
5.1.2 MMU Organization
Figure 5-1 shows the conceptual organization of a PowerPC MMU in a 32-bit
implementation; note that it does not describe the specific hardware used to implement the
memory management function for a particular processor. Processors may optionally
implement on-chip TLBs, hardware support for the automatic search of the page tables for
PTEs, and other hardware features (invisible to the system software) not shown.
The MPC750 maintains two on-chip TLBs with the following characteristics:
•
128 entries, two-way set associative (64 x 2), LRU replacement
Data TLB supports the DMMU; instruction TLB supports the IMMU
Hardware TLB update
Hardware update of referenced (R) and changed (C) bits in the translation table
In the event of a TLB miss, the hardware attempts to load the TLB based on the results of
a translation table search operation.
Figure 5-2 and Figure 5-3 show the conceptual organization of the MPC750 instruction and
data MMUs, respectively. The instruction addresses shown in Figure 5-2 are generated by
the processor for sequential instruction fetches and addresses that correspond to a change
of program flow. Data addresses shown in Figure 5-3 are generated by load, store, and
cache instructions.
As shown in the figures, after an address is generated, the high-order bits of the effective
address, EA[O-19] (or a smaller set of address bits, EA[O-n], in the cases of blocks), are
translated into physical address bits PA[O-19]. The low-order address bits, A[20-31], are
untranslated and are therefore identical for both effective and physical addresses. After
translating the address, the MMUs pass the resulting 32-bit physical address to the memory
subsystem.
5-4
MPC750 RISC Microprocessor User's Manual
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