Motorola MPC750 User Manual page 91

Table 2-4. HIDO Bit Functions (Continued)
Bit Name Function
22 SPD
Speculative cache access disable
a
Speculative bus accesses to nonguarded space (G
=
0) from both the instruction and data
caches is enabled
1 Speculative bus accesses to nonguarded space in both caches is disabled
23 IFEM Enable M bit on bus for instruction fetches.
a
M bit disabled. Instruction fetches are treated as nonglobal on the bus
1 Instruction fetches reflect the M bit from the WIM settings.
24 SGE Store gathering enable
a
Store gathering is disabled
1 Integer store gathering is performed for write-through to nonguarded space or for
cache-inhibited stores to nonguarded space for 4-byte, word-aligned stores. The LSU combines
stores to form a double word that is sent out on the 60x bus as a single-beat operation. Stores
are gathered only if successive, eligible stores, are queued and pending. Store gathering is
performed regardless of address order or endian mode.
25 DCFA Data cache flush assist. (Force data cache to ignore invalid sets on miss replacement selection.)
a
The data cache flush assist facility is disabled
1 The miss replacement algorithm ignores invalid entries and follows the replacement sequence
defined by the PLRU bits. This reduces the series of uniquely addressed load or debz
instructions to eight per set. The bit should be set just before beginning a cache flush routine
and should be cleared when the series of instructions is complete.
26 BTIC BTIC disable-used to disable use of the 64-entry branch instruction cache.
0 The BTIC is enabled and new entries can be added.
1 The BTIC contents are invalidated and the BTIC behaves as if it were empty. New entries
cannot be added until the BTIC is enabled.
27
-
Not used. Defined as FBIOB on earlier 603-type processors.
28 ABE Address broadcast enable-controls whether certain address-only operations (such as cache
operations, eieio, and sync) are broadcast on the 60x bus.
0 Address-only operations affect only local L 1 and L2 caches and are not broadcast.
1 Address-only operations are broadcast on the 60x bus. Affected instructions are eieio, sync,
debi, dcbf, and dcbs!. A sync instruction completes only after a successful broadcast.
Execution of eieio causes a broadcast that may be used to
prevent
any external
devices,
such
as a bus bridge chip, from store gathering.
Note that debz (with M
=
1, coherency required) always broadcasts on the 60x bus regardless of
the setting of this bit. An iebi is never broadcast. No cache operations, except debz, are snooped
by the MPC750 regardless of whether the ABE is set. Bus activity caused by these instructions
results directly from performing the operation on the MPC750 cache.
29 BHT Branch history table enable
0 BHT disabled. The MPC750 uses static branch prediction as defined by the PowerPC
architecture (UISA) for those branch instructions the BHT would have otherwise used to predict
(that is, those that use the CR as the only mechanism to determine direction). For more
information on static branch prediction, see "Conditional Branch Control:' in Chapter 4 of The
Programming Environments Manual.
1 Allows the use of the 512-entry branch history table (BHT).
The BHT is disabled at power-on reset. All entries are set to weakly, not-taken.
30
-
Not used
31 NOOPTI No-op the data cache touch instructions.
0 The debt and debtst instructions are enabled.
1 The debt and debtst instructions are no-oped globally.
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