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High Impedance-Occurs for at least one cycle when changing
between read and write operations to the L2 cache memory.
7.2.9.9.2 L2 Data (L2DATA[0-63])-lnput
Following are the state meaning and timing comments for the L2 data input signals.
State Meaning
AssertedlNegated-Represents the state of data during a data read
transaction; data is always transferred as double words.
Timing Comments AssertionlNegation-Driven valid by L2 cache memory during read
operations.
7.2.9.10 L2 Data Parity (L2DP[O-7])
The eight data bus parity (L2DP[0-7]) signals on the MPC750 are both output and input
signals.
7.2.9.10.1 L2 Data Parity (L2DP[O-7])-Output
Following are the state meaning and timing comments for the L2 data parity output signals.
State Meaning
AssertedlNegated-Represents odd parity for each of the 8 bytes of
L2 cache data during write transactions. Odd parity means that an
odd number of bits, including the parity bit, are driven high. Note
that parity bit 0 is associated with bits 0-7 (byte lane 0) of the
L2DATA bus.
Timing Comments
AssertionlNegation-The same as L2DATA[0-63].
High Impedance-The same as L2DATA[0-63].
7.2.9.10.2 L2 Data Parity (L2DP[O-7])-lnput
Following are the state meaning and timing comments for the L2 parity input signals.
State Meaning
AssertedlNegated-Represents odd parity for each byte of L2 cache
read data.
Timing Comments AssertionlNegation-The same as L2DATA[0-63].
7.2.9.11 L2 Chip Enable (L2CE)-Output
Following are the state meaning and timing comments for the L2CE signal.
State Meaning
Asserted-Indicates that the L2 cache memory devices are being
selected for a read or write operation.
Negated-Indicates that the MPC750 is not selecting the L2 cache
memory devices for a read or write operation.
Timing Comments AssertionlNegation-May occur on any cycle. L2CE is driven high
during HRESET assertion.
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MPC750 RISC Microprocessor User's Manual
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