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1.12 Performance Monitor
The MPC750 incorporates a performance monitor facility that system designers can use to
help bring up, debug, and optimize software performance. The performance monitor counts
events during execution of code, relating to dispatch, execution, completion, and memory
accesses.
The performance monitor incorporates several registers that can be read and written to by
supervisor-level software. User-level versions of these registers provide read-only access
for user-level applications. These registers are described in Section 1.4, "PowerPC
Registers and Programming Model." Performance monitor control registers, MMCRO or
MMCR1, can be used to specify which events are to be counted and the conditions for
which a performance monitoring interrupt is taken. Additionally, the sampled instruction
address register, SIA (USIA), holds the address of the first instruction to complete after the
counter overflowed.
Attempting to write to a user-read-only performance monitor register causes a program
exception, regardless of the MSR[PR] setting.
When a performance monitoring interrupt occurs, program execution continues from
vector offset OxOOFOO.
Chapter 11, "Performance Monitor," describes the operation of the performance monitor
diagnostic tool incorporated in the MPC750.
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MPC750 RISC Microprocessor User's Manual
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