Motorola MPC750 User Manual page 331

Normal termination of a burst transfer occurs when T A is asserted for four bus clock cycles,
as shown in Figure 8-11. The bus clock cycles in which TA is asserted need not be
consecutive, thus allowing pacing of the data transfer beats. For read bursts to terminate
successfully, TEA and DRTRY must remain negated during the transfer. For write bursts,
TEA must remain negated for a successful transfer. DRTRY is ignored during data writes.
2 3 4 5 6
7
Figure 8-11. Normal Burst Transaction
For read bursts, DRTRY may be asserted one bus clock cycle after TA is asserted to signal
that the data presented with TA is invalid and that the processor must wait for the negation
of DR TRY before forwarding data to the processor (see Figure 8-12). Thus, a data beat can
be terminated by a predicted branch with
'fA
and then one bus clock cycle later confirmed
with the negation of DRTRY. The DRTRY signal is valid only for read transactions. TA
must be asserted on the bus clock cycle before the first bus clock cycle of the assertion of
DRTRY; otherwise the results are undefined.
The DRTRY signal extends data bus mastership such that other processors cannot use the
data bus until DRTRY is negated. Therefore, in the example in Figure 8-12, DBB cannot
be asserted until bus clock cycle 6. This is true for both read and write operations even
though DRTRY does not extend bus mastership for write operations.
8-24
MPC750 RISC Microprocessor User's Manual