Motorola MPC750 User Manual page 174

Table 3-5. Response to Snooped Bus Transactions (Continued)
Snooped Transaction TT[O-4] MPC750 Response
TLB invalidate
11000 No action is taken.
External control word 11100 No action is taken.
read
Iwarx
reservation set 00001 No action is taken.
Reserved 00101
-
TLBSYNC 01001 No action is taken.
ICBI 01101
No action is taken.
Reserved 1XX01
-
Write-with-flush
00010 A write-with-flush operation is a single-beat or burst transaction
initiated when a caching-inhibited or write-through store instruction is
executed.
• If the addressed cache block is in the exclusive (E) state, the cache
block is placed in the invalid (I) state.
• If the addressed cache block is in the modified (M) state, the
MPC750 asserts ARTRY and initiates a push of the modified block
out of the cache and the cache block is placed in the invalid (I) state.
• If the address misses in the cache, no action is taken.
Any reservation associated with the address is canceled.
Write-with-kill 00110 A write-with-kill operation is a burst transaction initiated due to a
castout, caching-allowed push, or snoop copy -back.
• If the address hits in the cache, the cache block is placed in the
invalid (I) state (killing modified data that may have been in the
block).
• If the address misses in the cache, no action is taken.
Any reservation associated with the address is canceled.
Read 01010 A read operation is used by most single-beat and burst load
transactions on the bus.
For single-beat, caching-inhibited read transaction:
• If the addressed cache block is in the exclusive (E) state, the cache
block remains in the exclusive (E) state.
• If the addressed cache block is in the modified (M) state, the
MPC750 asserts ARTRY and initiates a push of the modified block
out of the cache and the cache block is placed in the exclusive (E)
state.
• If the address misses in the cache, no action is taken.
For burst read transactions:
• If the addressed cache block is in the exclusive (E) state, the cache
block is placed in the invalid (I) state.
• If the addressed cache block is in the modified (M) state, the
MPC750 asserts ARTRY and initiates a push of the modified block
out of the cache and the cache block is placed in the invalid (I) state.
• If the address misses in the cache, no action is taken.
Chapter 3. L 1 Instruction and Data Cache Operation 3-27