Late-Write Sram - Motorola MPC750 User Manual

Figure 9-6 shows a burst read-modify-write memory access sequence when the L2 cache
interface is configured with pipelined burst SRAM.
SRAMClk
I I
~
I I
L2CE
1\
I
I
I I \ I
~
I I I I I 1 I I I I I I I I I I I I
L2WE :
~ ~
: :
!
! : : : !
i \ I I I I I
rr-
~~burst rd~ ~burst rd~ -+-----rd modify w~ ~burst wr~'.
:
SRAMAddress
RD R1 R2 R3 R4 RS R6 R7 R8 R ' W9 W10 W11 W12 W13
SRAMMemory
SRAMData
Notes:
R drv indicates where some burst RAMs may begin driving the data bus.
R xtr indicates where an extra read cycle is signaled to keep the burst RAM driving the
data bus for the last read.
Figure 9-6. Burst Read-Modify-Write L2 Cache Access (Pipelined)
Figure 9-7 shows a burst read-write-write memory access sequence when the L2 cache
interface is configured with pipe lined burst SRAM.
SRAMClk
L2WE
SRAMAddress
SRAMMemory
SRAMData
I
Notes:
R drv indicates where some burst RAMs may begin driving the data bus.
R xtr indicates where an extra read cycle is signaled to keep the burst RAM driving the
data bus for the last read.
Figure 9-7. Burst Read-Write-Write L2 Cache Access (Pipelined)
9.1.7.3 Late-Write SRAM
Late-write SRAMs offer improved performance when compared to pipelined burst SRAMs
by·not requiring an extra read cycle during read operations, and requiring one cycle less
when transitioning from a read to write operation. Late-write SRAMs implement an
internal write queue, allowing write data to be provided one cycle after the write operation
is signaled on the address and control buses. In this way write operations are queued on the
address and data bus in the same way as read operations, allowing transitions between read
and write operations to occur more efficiently.
9-12 MPC750 RISC Microprocessor User's Manual