Mpc7S0 Microprocessor Exception Implementation - Motorola MPC750 User Manual

Asynchronous, maskable-The PowerPC architecture defines external and
decrementer interrupts as maskable, asynchronous exceptions. When these
exceptions occur, their handling is postponed until the next instruction, and any
exceptions associated with that instruction, completes execution. If no instructions
are in the execution units, the exception is taken immediately upon determination of
the correct restart address (for loading SRRO). As shown in Table 1-4, the MPC750
implements additional asynchronous, maskable exceptions.
Asynchronous, nonmaskable-There are two nonmaskable asynchronous
exceptions: system reset and the machine check exception. These exceptions may
not be recoverable, or may provide a limited degree of recoverability. Exceptions
report recoverability through the MSR[RI] bit.
1.7.2 MPC750 Microprocessor Exception Implementation
The MPC750 exception classes described above are shown in Table 1-4.
Table 1-4. MPC750 Microprocessor Exception Classifications
Synchronous/Asynchronous Precise/Imprecise Exception Type
Asynchronous, nonmaskable Imprecise Machine check, system reset
Asynchronous, maskable Precise External, decrementer, system management, performance
monitor, and thermal management interrupts
Synchronous Precise Instruction·caused exceptions
Although exceptions have other characteristics, such as priority and recoverability,
Table 1-4 describes categories of exceptions the MPC750 handles uniquely. Table 1-4
includes no synchronous imprecise exceptions; although the PowerPC architecture
supports imprecise handling of floating-point exceptions, the MPC750 implements these
exception modes precisely. Table 1-5 lists MPC750 exceptions and conditions that cause
them. Exceptions specific to the MPC750 are indicated.
Table 1-5. Exceptions and Conditions
Exception Type
Vector Offset
Causing Conditions
(hex)
Reserved 00000
-
System reset 00100 Assertion of either HRESET or SRESET or at power·on reset
Machine check 00200 Assertion of TEA during a data bus transaction, assertion of MCP, or an
address, data, or L2 bus parity error. MSR[ME] must be set.
OSI
00300
As specified in the PowerPC architecture. For TLB misses on load, store, or
cache operations, a OSI exception occurs if a page fault occurs.
lSI 00400 As defined by the PowerPC architecture.
External interrupt 00500 MSR[EE] : 1 and TNT is asserted.
Chapter 1. Overview
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