L2 Cache Operation - Motorola MPC750 User Manual

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L2ADDR[16-{)]
ADDR[16-0]
L2DATA[Q-63]
uptlOnal)
DATA[Q-31]
L2DPJQ:TI
PARITY[Q-3]
L2CE
E
128k x 36
L2WE
(Optional)
W
SRAM
L2ZZ
0- ADSC
1- ADSP
ZZ
L2CLK_OUTA
K
MPC750
ADDR[16-{)]
DATA[0-31]
L2SYNC OUT
I
PARITY[O-3]
L2SYNCJN
E
128kx36
W
SRAM
0- ADSC
1- ADSP
(Optional)
ZZ
L2CLK_OUTB
K
Notes:
- For a 1-Mbyte L2, use address bits 16-0 (bit 0 is LSB).
- For a 512-Kby1e L2, use address bits 15-0 (bit 0 is LSB).
- For a 256-Kby1e L2, use address bits 14-0 (bit 0 is LSB).
- External clock routing should ensure that the rising edge of the L2 clock is
coincident at the K input of all SRAMs and at the L2Sync_ln input of the
MPC750. The clock A network can be used solely or the clock B network can
also be used depending on loading, frequency, and number of SRAMs.
- No pull-up resistors are normally required for the L2 interface.
- The MPC750 supports only one bank of SRAMs.
- For high-speed operation, no more than two loads should be presented on each
L2 interface signal.
Figure 9-1. Typical 1-Mbyte L2 Cache Configuration
9.1.1 L2 Cache Operation
The MPC750's L2 cache is a combined instruction and data cache that receives memory
requests from both LI instruction and data caches independently. The LI requests are
generally the result of instruction fetch misses, data load or store misses, write-through
operations, or cache management instructions. Each LI request generates an address
lookup in the L2 tags. If a hit occurs, the instructions or data are forwarded to the LI cache.
A miss in the L2 tags causes the LI request to be forwarded to the 60x bus interface. The
cache block received from the bus is forwarded to the LI cache immediately, and is also
loaded into the L2 cache with the tag marked valid and unmodified. If the cache block
loaded into the L2 causes a new tag entry to be allocated and the current tag entry is marked
valid modified, the modified sectors of the tag to be replaced are castout from the L2 cache
to the 60x bus.
9-2
MPC750 RISC Microprocessor User's Manual

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