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During power-up or hard reset, all the valid bits of the blocks are cleared and the PLRU bits
cleared to point to block LO of each set. Note that this is also the state of the data or
instruction cache after setting their respective flash invalidate bit (HIDO[DCFI] or
HIDO[ICFI]).
3.5.2 Cache Flush Operations
The instruction cache can be invalidated by executing a series of icbi instructions or by
setting HIDO[ICFI]. The data cache can be invalidated by executing a series of debi
instructions or by setting HIDO[DCFI].
Any modified entries in the data cache can be copied back to memory (flushed) by using
the debf instruction or by executing a series of 12 uniquely addressed load or debz
instructions to each of the 128 sets. The address space should not be shared with any other
process to prevent snoop hit invalidations during the flushing routine. Exceptions should be
disabled during this time so that the PLRU algorithm does not get disturbed.
The data cache flush assist bit, HIDO[DCFA], simplifies the software flushing process.
When set, HIDO[DCFA] forces the PLRU replacement algorithm to ignore the invalid
entries and follow the replacement sequence defined by the PLRU bits. This reduces the
series of uniquely addressed load or debz instructions to eight per set. HIDO[DCFA] should
be set just prior to the beginning of the cache flush routine and cleared after the series of
instructions is complete.
3.5.3 Data Cache-Block-Fill Operations
The MPC750's data cache blocks are filled in four beats of 64 bits each, with the critical
double word loaded first. The data cache is not blocked to internal accesses while the load
(caused by a cache miss) completes. This functionality is sometimes referred to as 'hits
under misses,' because the cache can service a hit while a cache miss fill is waiting to
complete. The critical-double-word read from memory is simultaneously written to the data
cache and forwarded to the requesting unit, thus minimizing stalls due to cache fill latency.
A cache block is filled after a read miss or write miss (read-with-intent-to-modify) occurs
in the cache. The cache block that corresponds to the missed address is updated by a burst
transfer of the data from the L2 or system memory. Note that if a read miss occurs in a
system with multiple bus masters, and the data is modified in another cache, the modified
data is first written to external memory before the cache fill occurs.
3.5.4 Instruction Cache-Block-Fill Operations
The MPC750's instruction cache blocks are loaded in four beats of 64 bits each, with the
critical double word loaded first. The instruction cache is not blocked to internal accesses
while the fetch (caused by a cache miss) completes. On a cache miss, the critical and
following double words read from memory are simultaneously written to the instruction
cache and forwarded to the instruction queue, thus minimizing stalls due to cache fill
latency. There is no snooping of the instruction cache.
Chapter 3. L 1 Instruction and Data Cache Operation
3-21
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