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The general functions and features of the bus interface are as follows:
Seven address register buffers that include the following:
-
Instruction cache load address buffer
-
Data cache load address buffer
-
Two data cache castout/store address buffers (associated data block buffers
located in cache)
-
Data cache snoop copy-back address buffer (associated data block buffer located
in cache)
-
Reservation address buffer for snoop monitoring
•
Pipeline collision detection for data cache buffers
•
Reservation address snooping for lwarxlstwcx. instructions
•
One-level address pipelining
•
Load ahead of store capability
A conceptual block diagram of the bus interface is shown in Figure 3-7. The address
register queues in the figure hold transaction requests that the bus interface may issue on
the bus independently of the other requests. The bus interface may have up to two
transactions operating on the bus at any given time through the use of address pipe lining.
-'
I-Cache
I.
I
I
.I
D-Cache
I~
•
I
•
•
i
BIU
H
I-Cache
II
D-Cache
liD-cache ) liD-cache
II
D-Cache
I
Control
LD Addr
LD Addr
CST/ST Addr 0
CST/ST Addr 1
SNP Addr
t
t
t
t
I
I
Snoop
Addr
1
Control
Addri
Data
Oat
a
L2 or System Bus
j
Figure 3-7. Bus Interface Address Buffers
For additional information about the MPC750 bus interface and the bus protocols, refer to
Chapter 8, "System Interface Operation."
Chapter 3. L 1 Instruction and Data Cache Operation
3-31
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