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7.2.9 System Status Signals
Most system status signals are input signals that indicate when exceptions are received,
when checkstop conditions have occurred, and when the MPC750 must be reset. The
MPC750 generates the output signal, CKSTP _OUT, when it detects a checkstop condition.
For a detailed description of these signals, see Section 8.7, "Interrupt, Checkstop, and Reset
Signals."
7.2.9.1 Interrupt (INT)-Input
Following are the state meaning and timing comments for the INT signal.
State Meaning
Asserted-The MPC750 initiates an interrupt if MSR[EE] is set;
otherwise, the MPC750 ignores the interrupt. To guarantee that the
MPC750 will take the external interrupt, INT must be held active
until the MPC750 takes the interrupt; otherwise, whether the
MPC750 takes an external interrupt depends on whether the
MSR[EE] bit was set while the INT signal was held active.
Negated-Indicates that normal operation should proceed. See
Section 8.7.1, "External Interrupts."
Timing Comments Assertion-May occur at any time and may be asserted
asynchronously to the input clocks. The INT input is level-sensitive.
Negation-Should not occur until interrupt is taken.
7.2.9.2 System Management Interrupt (SMI)-Input
Following are the state meaning and timing comments for SMI.
State Meaning
Asserted-The MPC750 initiates a system management interrupt
operation if the MSR[EE] is set; otherwise, the MPC750 ignores the
exception condition. The system must hold SMI active until the
exception is taken.
Negated-Indicates that normal operation should proceed. See
Section 8.7.1, "External Interrupts."
Timing Comments Assertion-May occur at any time and may be asserted
asynchronously to the input clocks. The SMI input is level-sensitive.
Negation-Should not occur until interrupt is taken.
7.2.9.3 Machine Check Interrupt (MCP)-Input
Following are the state meaning and timing comments for the MCP signal.
State Meaning
Asserted-The MPC750 initiates a machine check interrupt
operation if MSR[ME] and HIDO[EMCP] are set; if MSR[ME] is
cleared and HIDO[EMCP] is set, the MPC750 must terminate
operation by internally gating off all clocks, and releasing all outputs
(except CKSTP _OUT) to the high-impedance state. IfHIDO[EMCP]
Chapter 7. Signal Descriptions
7-21
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